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| SSCNE555 Elektronische Bauelemente RoHS Compliant Product Single Timer Description The SPNE555 is a highly stable timer IC that can be operated in astable mode and monostable mode. For monostable mode: time delay is controlled by one external and one capacitor. For stable mode: frequency and duty cycle are accurately controlled with two external resistors and one capacitor. Features High current driver capability (=200mA) Adjustable duty cycle timing form sec to hours turn off time less than 2 sec Package Dimensions Applications Precision timing Pulse generation Time delay generation REF. A B C D E F Millimeter Min. Max. 5.80 4.80 3.80 0C 0.40 0.19 6.20 5.00 4.00 8C 0.90 0.25 REF. M H L J K G Millimeter Min. Max. 0.10 0.25 0.35 0.49 1.35 1.75 0.375 REF. 45 C 1.27 TYP. Block Diagram and Simplified Application & Pin Configuration http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2006 Rev. A Page 1 of 5 SSCNE555 Elektronische Bauelemente Single Timer Absolute Maximum Ratings (Ta = 25 C) Parameter Supply Voltage Differential Input Voltage Input Voltage Power Dissipation Opearting, Storage Temperature Symbol VCC IO Tlead PD TOPR, TSTG Value 16 200 300 440 0~70, -65~150 Units V mA C mW C Electrical Characteristics (Ta = 25 C, VCC = 5 ~ 15V) Parameter Supply Voltage Supply Current (Note 1) Symbol Test Conditions Min 4.5 Typ 3 10 1.0 50 0.1 2.25 150 0.3 10.0 3.33 10.0 3.33 0.1 1.67 5 0.7 0.1 0.06 0.3 0.05 12.5 13.3 3.3 100 100 20 Max 16 6 15 11.0 4.0 10.8 3.55 0.25 2.2 5.6 2.0 1.0 0.4 0.25 0.75 0.35 15 5 100 Units V mA mA % ppm/C %/V % ppm/C %/V V A V A V VCC ICC ACCUR t/T t/VCC Timing Error (astable) VCC = 5V, RL = VCC = 15V, RL = Timing Error (monostable) RA = 1k ~ 100k C = 0.1 F - Initial Accurary (Note 1) Drift with Temperature Drift with Supply Voltage Initial Accurary (Note 1) Drift with Temperature Drift with Supply Voltage Control Voltage Threshold Voltage Threshold Current (Note 3) Trigger Voltage Trigger Current Reset Voltage ACCUR t/T t/VCC VC VTH ITH Vtr Itr Vrst RA = 1k ~ 100k C = 0.1 F VCC = 15V VCC = 5V VCC = 15V VCC = 5V 9.0 2.6 9.2 3.1 - VCC = 5V VCC = 15V Vtr = 0 1.1 4.5 0.4 - Reset Current Low Output Voltage Irst VCC = 15V, Isink = 10mA mA V VOL High Output Voltage VCC = 15V, Isink = 50mA VCC = 5V, Isink = 5mA VCC = 15V, Isink = 200mA VOH Reset Time of Output Fall Time of Output Discharge leakage Current VCC = 15V, Isink = 100mA VCC = 5V, Isink = 100mA 12.75 2.75 - V nSec nSec nA tR tF ILKG Note 1: Supply current when output is high typically 1 mA less at VCC = 5V Note 2: Tested at VCC = 5V and VCC = 15V. Note 3: This will determine the maximum value or RA+RB for 15V operation, the maximum total is R=20M, and for 5V operation the maximum total is R=6.7M. http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2006 Rev. A Page 2 of 5 SSCNE555 Elektronische Bauelemente Single Timer Characteristics Curve VCC = 15 V http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2006 Rev. A Page 3of 5 SSCNE555 Elektronische Bauelemente Single Timer http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2006 Rev. A Page 4 of 5 SSCNE555 Elektronische Bauelemente Single Timer Application Circuit FLIP-FLOP SPNE555 Application Notes The application circuit shows astable mode configuration. Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to VCC (Pin 8). The external capacitor C1 of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of GSCNE555, one input of the upper comparator is at voltage of 2/3VCC (R1=R2=R3), another input is connected to Pin 6. As soon as C1 is charging to higher than 2/3VCC, transistor Q1 is turned ON and discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One input of lower comparator is at voltage of 1/3VCC, discharge transistor Q1 turn off and C1 charges through RA and RB. Therefore, flip-flop circuit is set output high. That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is 0.693RB*C1. Vcc 1 Vcc Vcc 3 Vcc Vcc Vcc - 2 Vcc 3 In =0.693 T1=0.693*(RA+RB)*C1 T2=0.693*RB*C1 Thus the total period time T is given by T=T1+T2=0.693(RA+2RB)*C1 Then the frequency of astable mode is given by f= 1 T = 1.44 1.44 (RA+2RB)*C1 C1 The duty cycle is given by D.C. = T2 T = RB RB RA+2RB RA+2RB http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2006 Rev. A Page 5of 5 |
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